1. Field of the Invention
This invention relates to high density electronic packaging modules, and more particularly, to a three-dimensional multichip module comprised of memory and processor chips packaged in a single compact structure.
2. Description of the Related Art
To provide improved performance, manufacturers of integrated circuit chips continually strive to increase packaging density, which has led to the development of high density electronic packaging modules such as three-dimensional multichip structures. These multichip structures typically include a plurality of semiconductor chips that are adhered together in a stack so as to reduce the amount of space the chips occupy inside a system. It is generally understood that each chip in the stack has conductive leads that extend to one edge of the chip to provide electrical contact with external circuitry. Typically, a metallization pattern is provided on one side of the stack to establish electrical connection to circuitry external to the stack.
Disadvantageously, these multichip structures may not be suitable for IC chips that generate excessive heat during operation because it is difficult for heat to dissipate when the chips are sandwiched in a stack with other chips. Moreover, chips that generate excessive heat can transfer heat to adjacent chips in the stack and cause the adjacent chips to also overheat. Furthermore, the conventional multichip structures have limited space available on the side of the structure for interconnection wiring. As such, these structures may also not be suitable for chips that require numerous electrical connections to other chips in the same stack.
Thus, most conventional multichip modules are typically comprised of chips that perform essentially the same function because xe2x80x9csame functionxe2x80x9d chips generally do not require extensive interconnection with each other. For instance, the memory chips of a system are often incorporated into multichip structures because memory chips do not have to be extensively interconnected with each other. Furthermore, memory chips also tend not to generate excessive heat and are thus suitable for stack configuration.
Conversely, non-memory chips such as processor chips, logic chips, and A to D converter chips are usually not included as part of a multichip module because these chips generate higher heat per unit area and can be difficult to cool when sandwiched in a stack with other chips. In addition to cooling problems, processor chips, in particular, often require extensive interconnection with other chips in the module. In some instances, there is insufficient space on the multichip structure to accommodate all the necessary conductive leads required to interconnect the processor chips to various other chips in the module. Although through chip connections have been proposed to make inter-chip connections, see for example, U.S. Pat. No. 5,270,261, the process of forming these connections adds to the cost and complexity of fabrication. In light of the foregoing disadvantages, processor chips and many other non-memory chips are typically not incorporated in conventional multichip modules.
However, as computerized instruments continue to decrease in size, it becomes more desirable to combine chips of an entire system, including memory, processor and logic chips into one compact structure. Hence, it will be appreciated that there is a need for a multichip structure that comprises chips of an entire system and can be installed into and removed from the system as a unit. To this end, there is a particular need for a multichip structure that combines memory and non-memory chips in the same structure in a manner such that these chips are conveniently interconnected with each other and there is adequate cooling for chips that generate large heat per unit area.
The aforementioned needs are satisfied by the device and process of the present invention which are directed to a multichip module that includes both memory and non-memory chips. In one aspect, the multichip module comprises a plurality of semiconductor chips that are stacked and secured together in a manner so as to form a base structure having a first lateral face that is comprised of a portion of each chip. An exterior chip is mounted to the base structure in a manner such that a first surface of the exterior chip is positioned adjacent the first lateral face and extends across at least a portion of the first lateral face.
In another embodiment, the first lateral face of the base structure further comprises a plurality of conductive contacts that are interconnected to circuits in at least some of the chips forming the base structure. The conductive contacts may comprise conductor ends that are configured to make contact with exposed conductive elements formed on the first surface of the exterior chip when the exterior chip is mounted to the base structure.
Preferably, the base structure of the multichip module has four lateral faces wherein each lateral face is comprised of a portion of each chip in the base structure. Furthermore, a plurality of exterior chips are mounted to three of the lateral faces in a manner such that a first surface of each exterior chip is positioned adjacent the respective lateral face and extends across at least a portion of the lateral face. The exterior chips can make electrical contact with the chips in the base structure via conductive contacts formed on the lateral faces. The exterior chips can also be connected to each other via wire bonding or other interconnection techniques.
In yet another embodiment, the base structure of the multichip module further comprises an upper face and a lower face wherein a fourth and a fifth exterior chip are mounted respectively to the upper and lower faces. Preferably, the chips are stacked in a manner such that the upper and lower faces of the base structure are formed by circuit containing, active surfaces of the chips located at the upper and lower ends of the base structure. In one embodiment, the chip located at the upper end of the structure is stacked back to back against the adjacent chip so that the active surface of the chip at the upper end forms the upper face of the structure while the chip at the lower end forms the lower surface of the structure. Furthermore, conductive elements formed on the fourth and fifth exterior chips are positioned adjacent at least some of the conductors on the upper and lower faces respectively so as to establish electrical interconnection.
Furthermore, the multichip module may also comprise an insulating material that is formed between a first surface of the fourth exterior chip and the upper face of the base structure. An insulating material can also be formed between a first surface of the fifth exterior chip and the lower face of the base structure. Preferably, the insulating layers comprise a foamed polymeric material having a plurality of enclosed regions of air that is less than the minimum distance separating adjacent conductors on the upper and lower faces of the base structure. The foamed polymeric material can also be treated so as to provide the material with hydrophilic properties. Preferably, the chips in the base structure perform substantially the same function. Preferably, the exterior chips of the multichip module comprises non-memory chips, such as processor chip, logic chips, or A to D converter chip. In one embodiment, the exterior chips can be interconnected to each other via edge C4 connections.
In another aspect, the invention is directed to a method of forming a multichip module. The method comprises securing together a plurality of semiconductor chips in a manner so as to form a base structure having at least one lateral face that is comprised of a portion of each chip. The method further includes forming a plurality of conductive contacts on the at least one lateral face wherein the conductive contacts provide connection between the chips and external circuitry. The method also includes securing an exterior chip to the at least one lateral face wherein the exterior chip extends across at least a portion of the lateral face.
In yet another aspect, the multichip module comprises memory and non-memory chips which, in combination, are sufficient to enable operation of a particular system. In one embodiment, the module comprises a plurality of memory chips forming a base structure wherein the base structure has a plurality of lateral faces and an upper and lower face. The module also comprises a plurality of non-memory chips that are mounted to the base structure in a manner such that each non-memory chip extends across at least a portion of the respective lateral face of the base structure. Preferably, the outer surface of each exterior chip is not in contact with other chips and is exposed for improved cooling. The non-memory chips may comprise processor chips, logic chips, and A to D converter chips. In another embodiment, the multichip module further comprises two additional non-memory chips that are positioned adjacent the upper and lower faces of the base structure. Preferably a plurality of conductive contacts are formed on the lateral faces of the base structure and a plurality of conductive elements are also formed on the first surface of the non-memory chips wherein the conductors are placed adjacent to the conductive elements to establish electrical connection between the memory chips and the non-memory chips.
In yet another aspect, the multichip module comprises a first plurality of chips having a first and a second side and at least one lateral edge wherein conductive elements are exposed on the at least one lateral edge of the first plurality of chips. Furthermore, the first plurality of chips are adhered together such that the at least one lateral edge of each of the plurality of chips define a lateral surface. The multichip module further includes a second chip having a first and a second surface wherein the first surface of the second chip is adhered to at least a portion of the lateral surface of the first plurality of chips wherein conductive elements are exposed on the first surface of the second chip. Furthermore, a conductive interconnect layer is interposed between the at least a portion of the lateral surface of the first plurality of chips and the first surface of the second plurality of chips. The conductive interconnect layer includes a pattern of conductive contacts that are connected to the conductive elements of the at least one lateral edge of the first plurality of chips and to the conductive elements on the first surface of the second chip so as to interconnect the conductive elements of the first plurality of chips to the conductive elements of the second chip.
Advantageously, the present invention provides densely packaged multichip structures that incorporates memory and non-memory chips in the same module. As such, chips of an entire system can be placed in the module so as to reduce the space occupied by the chips inside the system. Furthermore, the chips that generate high heat per unit area or require extensive interconnection with other chips in the module are positioned on the lateral faces of the base structure in a manner such that the outer surface of the chip is not in contact with other chips so as to permit improved cooling and more efficient wiring. These and other advantages of the present invention will become more fully apparent from the following description taken in conjunction with the accompanying drawings.